Sunday October 11, 15:00 - 17:25 CEST + 17:40 - 20:00 CEST
FD-1. Sense, Process, and Communicate: State-of-the-Art Design Techniques for the Internet of Everything
Un-Ku Moon, Matthew L. Johnston, Gabor C. Temes, Arun S. Natarajan (Oregon State University, USA)
Many recent applications in biomedical devices, Internet of Things, security systems, automotive instrumentation, and other important structures call for sensor networks. Applications in these areas require high-performance pervasive sensors with adequate energy/power sources, mixed-mode signal processing and digitization, and effective communication networks. This tutorial will broadly focus on challenges and opportunities in pervasive sensor networks. The first talk will discuss the implementation of CMOS-based sensor platforms and heterogeneous integration approaches for several optical, chemical, and biological sensing applications. This will be followed by a tutorial description of incremental analog-to-digital converters; these are particularly effective in sensor and actuator analog interfaces, where they can provide very high accuracy, low latency, and simple digital post-filtering, and are easily multiplexed for multi-sensor systems, such as imagers and brain wave detectors. The most recent implementations of such data converters will be discussed, along with the most efficient design techniques.
A recent innovation in the design of energy-efficient high-performance CMOS amplifiers was the introduction of ring amplifiers. The next tutorial will include a description of the operating principles and design of these circuits, along with various implementation examples relevant to low-power and high-resolution digitization of sensed parameters.
Wireless communication between sensor nodes and gateway is critical for practical network deployments. The last talk will focus on enabling battery-less sensor systems with wireless communication capabilities. We will present RF-powered wireless sensor nodes in the context of size and weight limitations, and present design approaches to maximize RF-energy harvesting. The underlying IC-antenna co-design techniques will also be translated to the design of low-power wake-up radios for low-power sensor networks.
- CMOS-Integrated Sensors and Heterogeneous Integration Approaches. Matthew L. Johnston
- Applications and Special Features of Incremental ADCs. Gabor C. Temes
- Ring Amplifier and Its Emerging Applications. Un-Ku Moon
- Wirelessly Powered Sensing and Communication for IoT. Arun S. Natarajan
Un-Ku Moon received degrees from the University of Washington, Cornell University, and the University of Illinois at Urbana-Champaign. He has been with Oregon State University since 1998. Before joining Oregon State, he was with Bell Labs. He has served in various roles in the integrated circuits community, including being the Editor-in- Chief of JSSC and TCAS-II. He currently serves as the Program Chair of 2020 ISSCC.
Matthew L. Johnston received the B.S. degree in electrical engineering from the California Institute of Technology and the M.S. and Ph.D. degrees in electrical engineering from Columbia University. He joined Oregon State University in 2014. He was previously co-founder and manager of research at Helixis, a Caltech-based spinout developing instrumentation for real-time DNA amplification, from 2007 until its acquisition by Illumina in 2010. His research focuses on the integration of sensors and transducers with active CMOS substrates, lab-on-CMOS platforms, stretchable circuits and sensors systems, and bio-energy harvesting. He is currently an Associate Editor of the IEEE Transactions on Biomedical Circuits and Systems and of the IEEE Open Journal of Circuits and Systems.
Gabor C. Temes held academic positions at the Technical University of Budapest, Stanford University, and the University of California, Los Angeles (UCLA). He worked in industry at Northern Electric R&D Laboratories, Ottawa, Canada, as well as at Ampex Corp. He is now a Distinguished Professor Emeritus of UCLA, and a Professor at Oregon State University. He received the IEEE Leon K. Kirchmayer Graduate Teaching Award in 1998, and the 2006 IEEE Gustav Robert Kirchhoff Award. He received the 2017 Semiconductor Industry Association – SRC University Researcher Award. He is a member of the National Academy of Engineering.
Arun S. Natarajan received the B.Tech. degree from the Indian Institute of Technology, Madras the M.S. and Ph.D. degrees from the California Institute of Technology. From 2007 to 2012, he was a Research Staff Member with IBM T.J. Watson Research Center and worked on mm-wave phased arrays for multi-Gb/s data links and airborne radar. He joined Oregon State University in 2012. His research is focused on RF, mm-wave and sub-mm-wave integrated circuits and systems for high-speed wireless communication and imaging. He has served on the Technical Program Committee of ISSCC, RFIC, CSICS and as an Associate Editor of the IEEE Transactions on VLSI Systems, and Guest Editor of the IEEE Journal of Solid-State Circuits. He is currently an Associate Editor of the IEEE Transactions on Microwave Theory and Techniques.
Sunday October 11, 15:00 - 17:25 CEST
HD-1a. Time-based ADCs for future Systems on Chip
Luis Hernandez (Univ. Carlos III, Madrid, Spain), Pieter Rombouts (Ghent Univ., Belgium), Georges Gielen (KUL, Belgium)
Analog-to-digital converters incorporating VCOs and TDCs are a good alternative to switched-capacitor Sigma- Delta modulators for low-power sensor, biomedical and communications applications. As main advantages, they are mostly digital and suitable to be integrated along with digital logic in a nanometer CMOS SoC. One of the main problems to their widespread use is their intrinsic differences to designing switched-capacitor circuits, which forces analog designers into a total paradigm change. The aim of this tutorial is to show the design methodology of such time-based ADCs from the basics to the latest developments. Most analog designers might notice some resemblance to PLL design. The tutorial will clearly highlight the differences to standard PLL circuit design and will illustrate the design methodology with practical circuit design examples.
Part I: VCO-ADC basics
- Time-based and VCO-ADCs from a signal processing perspective
- Quantization noise, thermal noise, flicker noise, phase noise (PSS) and clock jitter in VCO-ADCs
- Overview of VCO-ADC architectures
Part II: VCO-ADC circuits and systems
- Oscillators: ring oscillators and their design methodology; other oscillators
- Analog VCO coupling stages: gm, source follower, sensor-controlled oscillators
- Design techniques - practical example
- Closed-loop VCO-ADC architectures.
- Practical design cases
Luis Hernandez-Corporales received a MS (‘89) and PhD (’95) degrees in Telecommunication Engineering from the Polytechnic University of Madrid. He did a postdoctoral stay at the U.S. during 1996 at the ECE dept. of Oregon State University (OSU). In 1997 he joined the University Carlos III of Madrid where he is currently Full Professor of the Department of Electronic Technology and leads the mixed signal Microelectronic Design and Applications research group. His topics of interest focus on signal theory, mixed signal microelectronics and specifically data acquisition using sigma-delta modulation. He has published more than 150 scientific articles and holds 20 international patents. He is a member of the IEEE-CAS ASPTC comitee and has been associate editor of IEEE Transactions on Circuits and systems I and II for 8 years.
Pieter Rombouts was born in Leuven, Belgium, in 1971. He received the Engineering degree in Applied Physics and the Ph.D. degree in Electronics from Ghent University in 1994 and 2000, respectively. Since 1994, he has been with the Electronics and Information Systems Department at Ghent University, where he has been a Professor of analog electronics since 2005. His technical interests are signal processing, circuits and systems theory, analog circuit design, and sensor systems. The main focus of his research has been on A/D and D/A conversion. He has served or is currently serving as an Associate Editor for the IEEE Transactions on Circuits and Systems I, the IEEE Transactions on Circuits and Systems II and Electronics Letters.
Georges G. E. Gielen received the M.Sc. and Ph.D. degrees in Electrical Engineering from Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 1986 and 1990, respectively. In 1990, he was a Post-Doctoral Research Assistant and a Visiting Lecturer with the Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA, USA. Since 1991, he has been in the MICAS research group with the Department of Electrical Engineering (ESAT), KU Leuven, where he currently is a Full Professor. His research interests include the design and design automation (CAD) of analog and mixed-signal integrated circuits, including data converters and sensor readout circuits. He is a frequently invited speaker/lecturer and coordinator/partner of several (industrial) research projects in this area, including several European projects. He has (co-)authored 10 books and more than 600 papers in edited books, international journals and conference proceedings. He is Fellow of the IEEE since 2002, and received the IEEE CAS Mac Van Valkenburg career award in 2015. He is a 1997 Laureate of the Belgian Royal Academy of Sciences, Literature and Arts in the discipline of Engineering.
HD-2a. Brain-Inspired Computing: Models and Architectures
Keshab K. Parhi (Univ. of Minnesota, USA)
With exponential increase in the amount of data collected per day, the fields of artificial intelligence and machine learning continue to progress at a rapid pace with respect to algorithms, models, applications and hardware. In particular, deep neural networks have revolutionized the field by providing unprecedented human-like performance in solving many real-world problems such as image or speech recognition. There is also a significant research aimed at unravelling the principles of computation in large biological neural networks and, in particular, biologically plausible spiking neural networks. Research efforts are also directed towards developing energy- efficient computing systems for machine learning and AI. New system architectures and computational models from tensor processing units to in-memory computing are being explored. Reducing energy consumption requires careful design choices from many perspectives. Some examples include: choice of model, approximations of the models for reduced storage and memory access, choice of precision for different layers of networks and in-memory computing. The half- day tutorial will provide a detailed overview of the new developments related to brain-inspired computing models and their energy-efficient architectures. Specific topics include: (a) Computing models: Perceptrons, convolutional neural networks, recurrent neural networks, spiking neural networks, Boltzmann machines, hyper-dimensional computing; (b) backpropagation for training, (c) Computing architectures: systolic arrays for convolutional neural networks, low-energy accelerators via sparsity, tensor decomposition, and quantization, in-memory computing.
- Computing Models: Perceptrons, multi-layer perceptrons, convolutional neural networks, recurrent neural networks: long short-term memory and gated recurrent units, spiking neural networks, Hopfield networks, Boltzmann machines and restricted Boltzmann machines, hyper-dimensional computing.
- Training: Review of back-propagation
- Computing Architectures: Systolic arrays for convolutional neural networks, computer architectures for spiking neural networks, low-energy neural network accelerators via sparsity, tensor decomposition, and quantization, and in-memory computing.
Keshab K. Parhi received the B.Tech. degree from the Indian Institute of Technology (IIT), Kharagpur, in 1982, the M.S.E.E. degree from the University of Pennsylvania, Philadelphia, in 1984, and the Ph.D. degree from the University of California, Berkeley, in 1988. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor and Edgar F. Johnson Professor of Electronic Communication in the Department of Electrical and Computer Engineering. He has published over 650 papers, is the inventor of 31 patents, and has authored the textbook VLSI Digital Signal Processing Systems (Wiley, 1999). His current research addresses VLSI architecture design of machine learning systems, hardware security, data-driven neuroscience and molecular/DNA computing. Dr. Parhi is the recipient of numerous awards including the 2017 Mac Van Valkenburg award and the 2012 Charles A. Desoer Technical Achievement award from the IEEE Circuits and Systems Society, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, and a Golden Jubilee medal from the IEEE Circuits and Systems Society in 2000. He served as the Editor-in-Chief of the IEEE Trans. Circuits and Systems, Part-I during 2004 and 2005. He was elected a Fellow of the IEEE in 1996 and a Fellow of the American Association for the Advancement of Science (AAAS) in 2017.
HD-3a. Microelectronics for DNA detection: From Sensors to Rapid Diagnostic Systems using CMOS Ion-Sensitive Field Effect Transistors
Pantelis Georgiou, Nicolas Moser (Imperial College London, UK)
The future of healthcare relies on the integration of personalised medicine in our daily lives, identifying illnesses rapidly and providing data to assist doctors in deciding on a suitable treatment. One avenue of research for such technology involves leveraging on the semiconductor industry, where advances have allowed to continuously push down the boundaries of scalability, robustness, computational power, affordability and miniaturisation. Sensors implemented in a Complementary Metal-Oxide-Semiconductor (CMOS) process have shown promises for integration with computational processing hardware on the same substrate. This has been the case for the Ion- Sensitive Field-Effect Transistors (ISFETs), which rely on a similar structure to the standard MOSFET and as such can be included as part of classical CMOS analogue front-end architectures. Thousands or millions of these sensors can then be integrated on the same microchip, leading to the design of full System-on-Chip (SoC) architectures for real-time ion imaging.
This tutorial will discuss implementation of the ISFET in unmodified CMOS technology, emergent trends in ISFET instrumentation and successful cases of integrated ISFET-based Lab-on-Chip (LoC) platforms. It consists of four parts:
• ISFET physics, operation and non-idealities in unmodified CMOS
• Design of analogue ISFET front-end architectures
• Methods for addressing ISFET non-idealities
• Integrated ISFET-based LoC systems for DNA based diagnostic systems
At the end of the tutorial, the attendees will have a solid understanding of the state-of-the-art of ISFET-based integrated circuits as part of full SoCs.
Part I: The ISFET as a CMOS Ion Sensor
- Opportunities for CMOS sensing
- Fundamentals of ISFET operation in unmodified CMOS
- ISFETs in weak inversion for low power operation
- Sensor non-idealities
Part II: Analogue Front-End Architectures
- Differential measurements
- Single measurements
- Voltage mode readout
- Current mode readout
- In-pixel quantisation
Part III: Circuit Strategies for Sensor Calibration
- Sensor adaptation
- Programmable-gate (PG) ISFET
- Gate reset
- Other techniques
- System compensation
- Baseline frame calibration
- Correlated Double Sampling (CDS)
Part IV: Integrated SoCs for diagnostics
- Large scale ISFET arrays for healthcare applications
- A Case Study : Ion Torrent for Full Genome Sequencing
- A Case Study : Handheld Technology for DNA-based Diagnostics
- Arising Challenges for LoC Integration
Pantelis Georgiou currently holds the position of Reader (Associate Professor) in Biomedical Electronics at Imperial College London within the Department of Electrical and Electronic Engineering. He is the head of the Bio-inspired Metabolic Technology Laboratory in the Centre for Bio-Inspired Technology; a multi-disciplinary group that invents, develops and demonstrates advanced micro-devices to meet global challenges in biomedical science and healthcare. His research includes ultralow power microelectronics, bio-inspired circuits and systems, lab-on-chip technology and application of micro-electronic technology to create novel medical devices. Application areas include new technologies for treatment of diabetes such as the artificial pancreas, novel Lab-on-Chip technology for genomics and diagnostics targeted towards infectious disease and antimicrobial resistance (AMR), and wearable technologies for rehabilitation of chronic conditions.
Dr. Georgiou graduated with a 1st Class Honours MEng Degree in Electrical and Electronic Engineering in 2004 and Ph.D. degree in 2008 both from Imperial College London. He then joined the Institute of Biomedical Engineering as Research Associate until 2010, when he was appointed Head of the Bio-inspired Metabolic Technology Laboratory. In 2011, he joined the Department of Electrical & Electronic Engineering, where he currently holds an academic faculty position. He has made significant contributions to integrated chemical-sensing systems in CMOS, conducting pioneering work on the development of ISFET sensors, which has enabled applications, such as point-of-care diagnostics and semiconductor genetic sequencing and has also developed the first bio-inspired artificial pancreas for treatment of Type I diabetes using the silicon-beta cell. Dr. Georgiou is a senior member of the IEEE and IET and serves on the BioCAS and Sensory Systems technical committees of the IEEE CAS Society. He is an associate editor of the IEEE Sensors and TBioCAS journals. He is also the CAS representative on the IEEE sensors council. In 2013 he was awarded the IET Mike Sergeant Achievement Medal for his outstanding contributions to engineering and leading a multidisciplinary team to deliver innovative medical devices. In 2017, he was also awarded the IEEE Sensors Technical Achievement award in the area of Sensor systems for significant contributions in bioelectronics, and in 2018 he was awarded the Rosetrees Trust Interdisciplinary Award for the development of a rapid diagnostic test to accurately detect bacterial infection in children using microchip technology. He is also an IEEE Distinguished Lecturer in Circuits and Systems.
Nicolas Moser received the M.Sc. degree in analogue and digital integrated circuit design, M.Res. degree in advanced computing and Ph.D. degree focussed on in-pixel quantisation methodologies for ISFET arrays from the Department of Electrical and Electronic Engineering, Imperial College London (ICL), London, U.K. in 2014, 2015 and 2019 respectively.
He is currently a Research Associate with the Department of Electrical and Electronic Engineering, ICL, in the Centre for Bio- Inspired Technology. He was awarded the EPSRC postdoctoral fellowship to further pursue his research towards the field of diagnostics. He is currently developing the next generation of point-of-care devices for rapid diagnosis of infectious diseases (dengue, malaria, tuberculosis …) in remote areas of low- and middle-income countries, addressing issues raised by the WHO. He is the author or co-author of 18 scientific publications.
Sunday October 11, 17:40 - 20:00 CEST
HD-1b. Low-Power ADCs with Time-Domain Techniques
Qiang Li (Univ. of Electronic Science and Technology of China), Franco Maloberti (Univ. of Pavia, Italy)
This tutorial addresses the low-power ADC design perspectives with a focus on time-domain ADCs in nanometer CMOS technologies. The tutorial is divided into two parts. In the first part, the low-power ADC design perspectives will be overviewed, including the fundamentals, architectures and low-power considerations on the block level and circuit level. In the second part, the ADC design with time-domain signaling will be discussed, starting from an overview of state-of-the-art time-based ADCs, including TDC-based, VCDL-based and VCO-based. Unique properties of time-domain quantizers will be studied, i.e., intrinsic noise shaping in delta-sigma modulators, inherent coarse quantization in Nyquist converters, metastability, trade-off flexibilities, etc. The number of oscillation cycles (NOC) are analyzed and exploited as an additional design space without extra cost in speed, power, and noise. Design examples using NOC to enhance the performance, efficiency, calibration and PVT robustness of VCO-based ADCs will be discussed.
- Low-power ADC design perspectives: fundamentals, architectures and LP
- Time-domain ADC design techniques: TDC-, VCDL- and VCO-based
- Time-domain quantizers
- Design examples, efficiency, calibration and PVT robustness of VCO-based ADCs
Qiang Li received the B.Eng. degree in electrical engineering from Huazhong University of Science and Technology, Wuhan, China, in 2001, and the Ph.D. degree from Nanyang Technological University, Singapore, in 2007.
Since 2001, he has been working on analog/RF circuits in both academia and industry, holding positions of Engineer, Project Leader, and Technical Consultant in Singapore, and Associate Professor in Denmark. He is currently a Full Professor with the University of Electronic Science and Technology of China, Chengdu, China, heading the Institute of Integrated Circuits and Systems. His research interests include low-voltage and low-power analog/RF circuits, data converters, and mixed-mode circuits for biomedical and sensor interfaces. (website: https://analog.casa)
Dr. Li was a recipient of the Young Changjiang Scholar Award in 2015 and the UESTC Teaching Excellence Award in 2011. He serves on the Student Research Preview (SRP) Committee of ISSCC, the Technical Program Committee of ESSCIRC and ASSCC, and was the TPC Chair of 2018 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS). He serves as a Guest Editor of IEEE Transactions on Circuits and Systems I (TCAS-I) and Associate Editor of IEEE Open Journal of Circuits and Systems (OJCAS). He is the Founding Chair of IEEE CASS/SSCS Chengdu Chapter.
Franco Maloberti received the Laurea Degree in Physics (Summa cum Laude) from the University of Parma, Italy, and the Dr. Honoris Causa degree in Electronics from the Inaoe, Puebla, Mexico.
He was a Visiting Professor at ETH-PEL, Zurich and at EPFL-LEG, Lausanne. He was the TI/J.Kilby Analog Engineering Chair Professor at the Texas A&M University and the Distinguished Microelectronic Chair Professor at University of Texas at Dallas. He is Emeritus Professor at the University of Pavia, Italy. He is Honorary Professor, University of Macau, Macau, China SAR. His professional expertise is in the design, analysis and characterization of integrated circuits and analogue digital applications, mainly in the areas of switched capacitor circuits, data converters, interfaces for telecommunication and sensor systems, and CAD for analogue and mixed A-D design.
He has written more than 570 published papers, seven books and holds 33 patents. He is the Chairman of The Academic Committee of the Microelectronics Key Lab. Macau, China. He is the Past President of the IEEE CAS Society (2017-18) and President (2015- 16), he was VP Region 8 of IEEE CAS (1995-1997), Associate Editor of IEEE-TCAS-II, President of the IEEE Sensor Council (2002-2003), IEEE CAS BoG member (2003-2005), VP Publications IEEE CAS (2007-2008). He was DL IEEE SSC Society (2009-2010) and DL IEEE CAS Society (2006-2007; 2012-2013). He received the 1999 IEEE CAS Society Meritorious Service Award, the 2000 CAS Society Golden Jubilee Medal, and the IEEE Millenium Medal. He received the 1996 IEE Fleming Premium, the ESSCIRC 2007 Best Paper Award and the IEEJ Workshop 2007 and 2010 Best Paper Award. He received the IEEE CAS Society 2013 Mac Van Valkenburg Award. He is an IEEE Life Fellow.
HD-2b. Silicon-Photonic/CMOS Receiver Design for Energy-Efficient Short-Reach Optical Links with High Bandwidth Density
Glenn Cowan & Diaaeldin Abdelrahman (Concordia University, Canada), Odile Liboiron-Ladouceur & Bahaa Radi (McGill University, Canada)
This tutorial presents the fundamentals of short-reach optical communication and the design of optical receivers needed to support future datacom requirements such as cost, latency, energy-efficiency, and bandwidth density. Optical links are widely deployed in data centers for links above a few meters. As data rates increase electrical links are being replaced with optical links over shorter and shorter distances with the goal of bringing the optical signal closer to the processor and memory chips. Different approaches for packaging and integration are explained along with their typical link budget. Recent advancements in photonic integration for receivers exploiting Silicon-on-Insulator (SOI) fabrication processes will presented. Examples of Silicon-Photonic(SiPh)/CMOS co-design solutions will be presented. The conflicting requirements of low power and low noise are explained as well as an overview of noise analysis. Emerging receiver architectures that give higher gain, lower noise but introduce inter- symbol interference will be presented. Attendees will also have an overview of the state of the art in receivers for PAM2 and PAM4 modulation in Silicon Photonic and Vertical cavity surface emitting laser (VCSEL)-based links.
- Introduction to wireline communication
- Modulation formats (Pulse amplitude modulation (PAM) 2 and 4)
- Frequency content of signals and typical bandwidth requirements
- Signal characterization, unit-pulse response, eye diagrams, inter- symbol interference
- Impact of frequency dependent losses in electrical links
- Noise and bit-error ratio
- Introduction to optical communication
- Typical block diagram of an optical link
- Link budget
- Types of optical fiber (Multi-mode and single-mode fiber)
- Optical-to-electrical conversion through photodiodes including their circuit models
- Current-to-voltage conversion with a resistor, noise/gain trade-offs
- Introduction to Silicon Photonics (SiPh) for data communications
- Silicon-on-Insulator fabrication process
- SiPh based transceivers – current state of the art
- SiPh based receivers
- SiPh/CMOS receiver designs
- Optical receiver design considerations
- Transimpedance amplifiers and the transimpedance limit
- Noise optimization
- Main-amplifier design – overview of cascaded stages and broadband techniques
- Motivation and introduction of low-bandwidth optical receivers
- General trade-offs of an inverter-based TIA
- Introduction of notion of effective gain
- Operation of equalizer-based receivers, contrasting the role of equalization here to the case in electrical links
- Noise comparison of architectures
- State of the art and design considerations for future optical receivers
- Examples of silicon-photonic integration
- Multi-mode fiber links
- All-Si optical receivers
- Receivers for PAM4.
Glenn Cowan received the B.A.Sc. degree from the University of Waterloo, Waterloo, ON, Canada in 1999, and the M.S. and Ph.D. degrees from Columbia University, New York, NY, in 2001 and 2005, respectively. During his graduate studies, he interned with Philips Research, Briarcliff Manor, NY. In 2005, he joined the Communications Technology Department at the IBM T. J. Watson Research Center, Yorktown Heights, NY. His research activities included CMOS circuits for high-speed communication, design for manufacturability, and circuits for the measurement of process variability. In 2007, he joined the Department of Electrical and Computer Engineering at Concordia University in Montreal, QC, Canada, where he is now a Professor. He was the 2005 recipient of Columbia’s Eliahu I. Jury award for outstanding achievement by a graduate student in the areas of systems, communications, or signal processing. His current research activities include low-power mixed-signal circuits for wireless, wireline, and optical communication, as well as mixed-signal computation.
Diaaeldin Abdelrahman received the B.Sc. degree in electrical engineering and the M.Sc. degree in electronics and communications from Assiut University, Asyut, Egypt, in 2010 and 2015, respectively. He is currently working toward the Ph.D. degree in electrical and computer engineering in the Integrated Circuit Design Group, Concordia University, Montreal, QC, Canada. His current research interests include highperformance integrated circuits for optical links.
Odile Liboiron-Ladouceur received the B.Eng. degree in electrical engineering from McGill University, Montreal, QC, Canada, in 1999, and the M.S. and Ph.D. degrees in electrical engineering from Columbia University, New York, NY, USA, in 2003 and 2007, respectively. From 1999 to 2000, she worked at Teradyne Inc. as an Applications Engineer in the mass storage business unit. She then joined Texas Instruments Incorporated in 2000 and spent two years working in the fiber optic business unit as a test and design engineer. She joined the Department of Electrical and Computer Engineering in 2008, and is currently an Associate Professor and Canada Research Chair in Photonics Interconnect. From 2009 to 2016, she was an associate editor for the IEEE Photonics Technology Letter. She was an elected member on the IEEE Photonics Society Board of Governance from 2016 to 2018. She was the general co-chair of Photonics in Switching and Computing (PSC) in 2017, 2019, and 2020. She holds six granted U.S. patents and coauthored over 60 peer-reviewed journal papers and more than 100 papers in conference proceedings. She published four book chapters and gave over 15 presentations as an invited speaker at international conferences. Her research interests include optical systems, photonic-integrated circuits, and photonic interconnects. She is the 2018 recipient of McGill Principal’s Prize for Outstanding Emerging Researcher. She manages the Photonic DataCom Research Team at McGill University.
Bahaa Radi received the B.S. degree in electrical engineering from The Hashemite University, Zarqa, Jordan in 2012 and the M.S. degrees in microsystems engineering from Masdar Institute (Now Khalifa University), Abu Dhabi, UAE in 2015. He is currently pursuing the Ph.D. degree in electrical engineering with the Photonic Systems Group, McGill University, Montreal, QC, Canada. His current research interests include power-efficient optical receivers, energy-efficient optical systems for short-reach applications, and electronic and photonic integrated circuits.
HD-3b. Neuromorphic Computing: Devices, Circuits and Algorithms
Vishal Saxena (Univ. of Delaware, USA)
There is a growing need for entirely new paradigms of computing that “can proactively interpret and learn from data, solve unfamiliar problems using what it has learned, and operate with the energy- efficiency of the human brain.” In alignment with this goal, large-scale integration of CMOS mixed- signal integrated circuits and nanoscale emerging devices, such as the phase-change (PCRAM) and resistive RAM (RRAM), etc., can enable a new generation of Neuromorphic computers that can be applied to a wide range of machine learning problems. This tutorial combines an overview of recent advances in energy-efficient Neuromorphic Computing Circuits and Systems for embedded deep learning applications. The tutorial aims to provide a complete picture to the audience; from emerging devices, to transistor-level neural circuit design, and learning algorithms to put the system together. Case studies will be presented for Neuromorphic System-on-a-chip (NeuSoC) with applications to spike-based machine learning followed by recent advances in the area spiking neural networks and neuromorphic hardware.
Part I: NEUROMORPHIC COMPUTING USING EMERGING DEVICES
- Review of Deep Learning and Neuromorphic Computing:
- Brief overview of recent trends in deep learning neural networks (feedforward, ConvNets, etc) and their associated energy consumption challenges.
- Spiking neural networks (SNNs) for achieving energy-efficiency: Digital VLSI and mixed-signal approaches and their comparison. Spike-timing dependent plasticity (STDP) and spike-based learning. Overview of existing hardware platforms such as IBM TrueNorth and Intel LoiHi and SpiNNaker.
- Leveraging Emerging Devices and Materials:
- Opportunities and results with emerging memory crossbars for implementing synapses in spiking neural networks. Overview of device types (memristors, Floating-gate, RRAM, PCRAM, STTRAM), operation, electrical waveforms and in-situ STDP learning.
- Challenges with emerging memory devices, such as memristors, for large-scale Neuromorphic computing; and their mitigation using stochastic and binary learning approaches.
- Energy-efficiency computation for NeuSoCs using emerging NVM devices. 1R vs 1T1R arrays for low power. Array architectures, sneak-path issue, basic circuit-device motif at the array level.
- Comparison of NVM technologies with respect to their suitability for neuromorphic computing.
Part II: NEUROMORPHIC COMPUTING CIRCUITS
- Ultra-low-power CMOS Neuron Circuits:
- Overview of contemporary neuromorphic neural circuits in standard CMOS, their limitations in driving resistive synapses. Literature survey and comparison of functionality and energy consumption.
- Review of recent work in this area. Event-driven CMOS Neurons and neural learning motifs that are compatible with dense crossbar arrays of emerging devices. VCO-based neurons.
- Energy-efficiency metrics and design tradeoffs for neurons and synapses.
- Neural Learning Motifs:
- Collection of neurons to form neural learning motifs: Winner-take-all (WTA), shared bus circuit architectures for semi-supervised learning.
Part III: SPIKE-BASED DEEP LEARNING ALGORITHMS AND CASE STUDIES
- Neuromorphic Deep Learning Algorithms: We will present an overview of recent results, including ours, that facilitate embedded mixed-signal deep learning:
- Fundamentals of integrate-and-fire neurons, plastic synapses, and their simulation using python-based tools. Winner-take-all spiking networks for unsupervised learning (including our results). Intuition behind powerful unsupervised learning in spike-based networks.
- Towards spike-based deep learning networks: Transfer learning of spiking deep learning networks. Recent results in event-based random backpropagation techniques, etc.
- System-level Aspects and Future Directions.
- Discussion on Emerging On-chip and off-chip interconnects for scaling the NeuSoC architectures. Available Neuromorphic devices.
- Future directions. Conclusion.
Vishal Saxena is an Associate Professor of Electrical and Computer Engineering at the University of Delaware. Earlier, he was the Micron Endowed Professor in Microelectronics and Associate Professor of Electrical and Computer Engineering at the University of Idaho and Boise State University. He obtained his B. Tech. degree in Electrical Engineering from Indian Institute of Technology, Madras in 2002. Subsequently, he graduated with a Ph.D. from Boise State University, ID in 2010 in the area of wideband Delta-Sigma ADC design. In between, he has held senior design position in broadband communication system design in a start-up, circuit design positions in Micron Imaging group (later Aptina) in Boise, ID and Lightwire Inc. in Allentown, PA. At University of Delaware, he directs the Analog Mixed-Signal and Photonic Integrated Circuits (AMPIC) Lab and teaches courses on Analog, Mixed-Signal, and RF IC design. Dr. Saxena received the prestigious 2015 NSF CAREER, 2016 AFOSR Young Investigator Program (YIP), and 2019 DARPA Young Faculty Award (YFA) awards. He was also recognized as 2016 Idaho’s accomplished under 40. He is a member of IEEE and has been an Associate Editor for IEEE TCAS-II journal. He currently serves on the steering committee of IEEE MWSCAS conference. His research interests include CMOS photonic interconnects, RF/mmWave photonics, data converters, Neuromorphic circuits and systems, and novel circuits for machine learning.
HD-4b. Wireless Integrated Micro-Sensors for in-vivo Healthcare Monitoring of Vital Physiological Biopotentials
Zheng Yuanjin (Nanyang Technological University, Singapore), Jiang Hanjun (Tsinghua University, Beijing, China)
Continuous health monitoring in hospital and/or home conditions has been of interest to doctors and healthcare practitioners for a long time. Recording of physiological and biopotential variables in real-life conditions could be especially useful in accurate management of chronic disorders or health problems, e.g., for stoke, shock, high blood pressure, diabetes, brain injury, indigestion, neural disorder, chronic pain, or severe obesity etc.. Physiological and biopotential signals have been used as important indicator of the vital signs of human-kinds, and real-time monitoring can predicate and be preventive to many serious life attacks. Furthermore, real-life long-term monitoring of health could be good measurement of treatment effects at home care, in situations where the subjects live their daily life. In this tutorial, firstly we will introduce and cover different types of physiological and biopotential signals such as electrocardiogram (ECG), blood oxygen saturation (SO2), neural spike, blood core temperature, Glucose, pH value, intracranial pressure, body sound, etc. Secondly, the typical and wireless integrated micro-sensor circuits and systems to acquire and measure the physiological signals are introduced and presented. Furthermore, the newly developed novel physiological sensors will be illustrated and demonstrated. The vital important applications and future development aspects are briefly envisioned.
This tutorial presents the acquisition and analysis of several types of physiological signals including ECG, neural spike, core temperature, SO2, glucose, intracranial pressure and bowel sound by wireless integrated micro-sensor circuits and systems.
- Introduction of wireless Integrated Micro-Sensor Circuits and Systems.
- Ultra-Wideband (UWB) and ULP high data rate transceivers for energy efficient communications.
- Integrated ECG sensor circuit and system.
- Wireless multi-sensor platform for WBAN.
- Wireless ingestible capsule circuits and systems.
- Wearable body sound monitoring and diagnosis circuit and system.
- Integrated neural recording and stimulation circuit and system.
- Implantable intracranial pressure sensing circuit and system.
- Non-invasive photoacoustic sensor (blood SO2, temperature and glucose) system.
- Application Envisions.
Yuanjin Zheng received his B.Eng. from Xian Jiaotong University, P. R. China in 1993 with the honor of the first class, M. Eng. from Xian Jiaotong University, P. R. China in 1996 with the honor of the best graduate student thesis award, and Ph.D. from Nanyang Technological University, Singapore in 2001. From July 1996 to April 1998, he worked at the national key lab of optical communication technology, university of electronic science and technology of china. He joined Institute of Microelectronics, A*STAR on 2001 and developed as a group technical manager. Since then, he has leaded in developing various wireless systems and CMOS integrated circuits, such as Bluetooth, WLAN, WCDMA, UWB, RF SAW/MEMS Radar, and wireless implant sensor and wearable interface circuits etc. Since July 2009, he joined Nanyang Technological University as an assistant professor and promoted to an associate professor in Feb. 2017, working on various radar system development and hybrid circuit and device (GaN, SAW, MEMS) designs, and flexible noninvasive sensor circuits and system for the applications of monitoring ECG, EEG, Spo2, SaO2, neural spike and blood glucose etc. He has authored or coauthored over 350 international journal and conference papers, 26 patents filed, and 5 book chapters. He is currently an associate editor of Journal of Circuits, Journal of X-Acoustics: Sensing and Imaging, and IEEE Trans. on Biomedical Circuit and Systems. He has been organizing several IEEE conferences as TPC Chairs and Session chairs.
Hanjun Jiang received the B.S. degree in electronic engineering from Tsinghua University, Beijing, China, in 2001, and the Ph.D. degree in electrical engineering from Iowa State University, Ames, IA, USA, in 2005. From 2005 to 2006, he was with Texas Instruments, Dallas, USA. He has been with the Institute of Microelectronics of Tsinghua University since 2007, where he is currently an Associate Professor. His current research interest mainly focuses in the area of low-power circuits and systems design, including the signal acquisition circuit, short-range transceiver and system-level integration, with an emphasis on the ingestible, wearable and implantable medical and healthcare applications. He has authored and co-authored over 100 peer-reviewed journal and conference papers, and contributed to 3 books. He holds more than 30 patents. He received the Science and Technology Award (1st place) from Chinese Institute of Electronics in 2018. Dr. Jiang was the IEEE Solid-State Circuits Society Beijing Chapter Chair from 2015 to 2018. He is currently a member of IEEE Biomedical and Life Science Circuits and Systems Technical Committee, and an Associate Editor of the IEEE Transactions on Biomedical Circuits and System.
HD-5b. Hardware and System Design Challenges for Secure Dependable Internet of Things
André N. Barreto, Padmanava Sen, Sebastian Haas (Barkhausen Institut, Dresden, Germany)
The tutorial will focus on different system requirements in the context of next-generation internet of things (IoT) systems, and how they present design challenges for the analog/RF and digital hardware. The presenters will explain the future challenges of connecting billions of devices to the internet and focus on the building blocks to enable a system that can ensure dependability and security. State-of-the-art approaches will be presented and key takeaways from ongoing research to enable systems in automotive and industry 4.0 applications will be derived. In that context, the research results from Barkhausen Institut will be explained along with evolving topics in this field being investigated around the world.
We will present three sessions in this topic. The first session will explain the dependability of IoT systems and present system challenges/open questions. The second session will focus on the analog hardware and mmWave design challenges. In the third session, we will explain the necessary application isolation on software and hardware level to reduce the impact of malicious attacks and present concepts to build secure multiprocessor systems for IoT platforms.
- Introduction and application scenarios (Dr.-Ing. André N. Barreto)
- What is meant by dependability for the IoT
- System Challenges and techniques at PHY and above
- Overview of applications and examples of relevant research topics
- RF hardware and phased array system integration in IoT applications (Dr. Padmanava Sen)
- Transceiver design challenges and solutions to enable mmWave operations
- Beamforming/phased array system implementation options in low-power IOT system context
- Overview of RF impairments and design of a transceiver to enable a joint Radar and communication platform for automotive applications
- Hardware security concepts in IoT processing platforms (Dr. -Ing. Sebastian Haas)
- Introduction: Exploiting HW/SW vulnerabilities with state-of-the-art malicious attacks and software faults
- Applying hardware security concepts to a multiprocessor platform with a tiled architecture: security-by-design, component isolation
- Security concepts on software level: microkernel-based operating systems with hardware- supported component isolation
André Noll Barreto (SM’11) received an M.Sc. from the Catholic University (PUC-Rio) in Rio de Janeiro, Brazil in 1996 and a Ph.D. from the Technische Universität Dresden, in Germany, in 2001, both in electrical engineering. After several positions in academia and industry in Switzerland (IBM Research) and Brazil (Claro, Nokia Technology Institute/INDT, Universidade de Brasília, Ektrum), he has joined in 2018 the Barkhausen Institut, in Dresden, Germany. He was Chair of the Centro-Norte Brasil Section of IEEE in 2013/2014 and General Co-Chair of the Brazilian Telecommunications Symposium in 2012. He is currently researching wireless communications for a reliable, resilient and secure Internet of Things.
Padmanava Sen (S’04-M’08-SM’15) received the B. Tech. degree in electronics and electrical communication engineering from the Indian Institute of Technology, Kharagpur, India, in 2003, and the M.S. and Ph.D. degrees from the Georgia Institute of Technology, Atlanta, GA, USA, in 2005 and 2007, respectively. In 2010, he joined Broadcom Corporation, Irvine, CA, USA, and worked in Broadcom for six years towards the development of phased array systems at 60GHz frequency bands (802.11ad). Apart from Broadcom Corporation (Irvine, USA and Bangalore, India), he worked in a 60 GHz startup Sayana Wireless in Atlanta for three years and IBM Corporation in Vermont, USA, for one year. He has joined in 2018 the Barkhausen Institut, in Dresden, Germany. He is currently leading the RF design enablement group at Barkhausen Institut, Dresden, Germany. He has authored or coauthored over 40 IEEE journal and conference papers. He holds three issued U.S. patents. He has contributed in multiple IEEE conferences as session co-chair and TPC member.
Sebastian Haas received his Dipl.-Ing. (M.Sc.) degree in Electrical Engineering in 2013 and his Dr.-Ing. (Ph.D.) in 2019 both from Technische Universität Dresden, Germany. From 2013 to 2019 he has been with the Vodafone Chair at Technische Universität Dresden, where he was working in the hardware design group. He was involved in the development of novel multiprocessor platforms, starting from the architectural design and implementation towards chip design and tape-out. Currently he is a research associate at Barkhausen Institut gGmbH, Dresden, Germany. His research interests include secure and energy-efficient hardware architectures in multiprocessor system-on-chips for the internet of things.
Sunday October 18, 15:00 - 17:25 CEST
HD-1c. Always-On Integrated Circuits and Systems down to nWs – Enabling a Greener and Smarter World with Nearly No Batteries
Massimo Alioto (National University of Singapore)
Batteries are well known to pose fundamental threats to the further advancement of systems for ubiquitous sensing and intelligence (e.g., Internet of Things, devices for healthcare, smart objects/systems). Batteries are indeed a major cost and form factor bottleneck in single-chip integrated systems, and will also have a heavy environmental impact when deployed (and disposed) at the expected scale of one trillion connected devices. Accordingly, research programs and startups focusing on battery-lightweight or battery- less operation have recently flourished, aiming to enable a new breed of integrated systems with millimeter-range form factor, always-on operation, and sub-dollar cost.
In this tutorial, the principles and the available state-of-the-art techniques for battery-lightweight and battery-less integrated systems with always-on operation are introduced. From a top-down viewpoint, system architectures are introduced to enable continuous adaptation to workload, harvested power/battery energy availability and targeted output quality, under limited or no battery energy. Time- and event-driven frameworks are introduced and exemplified with several silicon demonstrations, along with duty-cycled and always-on schemes. From a bottom-up perspective, circuit principles and advanced techniques are introduced to enable uninterrupted operation under an uncommonly wide range of available harvested power, and/or very limited battery energy. The tutorial covers all major sub-systems along the on-chip signal chain, from energy harvesting to power delivery, analog interfaces, digital processing, and higher-level signal sense-making. Edge computing, machine intelligence and in-memory computing are shown to be crucial in the enablement of continuous event monitoring and efficient energy usage at the system level. The related concepts are exemplified by integrated prototypes from industry and academia, both in bulk and FD-SOI technologies. Experimental results from internal research are also shared to gain a deeper insight into available opportunities in battery-less integrated systems.
At the end of the tutorial, the attendees will gain a solid understanding of the fundamental requirements, the basic design principles, and the state of the art in battery-lightweight or battery-less systems.
- APPLICATIONS AND SYSTEM-LEVEL INSIGHTS
- Energy sources in self-powered integrated systems
- Applications, trends and limitations of battery-powered integrated systems
- Always-on vs duty cycled system architectures
- Time-driven vs event-driven system architectures
- System-level metrics and requirements for battery-lightweight and battery-less operation
- Summary case study: battery-less sensor node for always-on environmental monitoring
- BUILDING BLOCKS AND CIRCUIT TECHNIQUES FOR MOSTLY- AND PURELY-HARVESTED SYSTEMS
- Fundamental design tradeoffs (sleep/active/wakeup energy, dynamic vs leakage power, communication vs computation, processing vs storage, general-purpose vs application-specific, ...)
- Key sub-systems design targets and design interactions
- Integrated harvesters, scaling trends and comparison
- Circuits for DC and AC harvesting and power conversion/delivery with ultra-wide power range (SISO/SIMO/SIMIMO inductive, capacitive, LDO, rectifiers, MPPT schemes, reconfigurable harvesters...)
- Summary case study: multi-source sensor node for always-on environmental monitoring
- CIRCUIT TECHNIQUES FOR ULTRA-WIDE POWER-PERFORMANCE TRADEOFF
- Sensor interfaces with ultra-wide power scalability: principles and state of the art
- Processing with ultra-wide power scalability: traditional voltage scaling and beyond
- Machine learning for signal monitoring and event detection: accelerators and in-memory computing
- Ultra-low power always-on peripheral circuits (timekeeping, voltage/temperature sensing, retentive
storage, self-tuning techniques for design margin elimination)
- Feedback schemes for adaptation to workload, power availability and output quality target
- Video demo: battery-less system with power down to nWs (active) and pWs (sleep)
- Summary of key metrics and trends
- Challenges and opportunities in next-generation integrated systems with little or no battery assistance
- To probe further
Massimo Alioto (M’01–SM’07-F’16) received the Laurea (MSc) degree in Electronics Engineering and the Ph.D. degree in Electrical Engineering from the University of Catania (Italy) in 1997 and 2001, respectively. He is with the Department of Electrical and Computer Engineering, National University of Singapore where he leads the Green IC group and is the Director of the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan Ann Arbor (2011-2012), BWRC – University of California, Berkeley (2009-2011), and EPFL (Switzerland, 2007).
He has authored or co-authored more than 280 publications on journals and conference proceedings. He is co-author of four books, including the first book on integrated circuit and system design for the IoT (Enabling the Internet of Things - from Circuits to Systems, Springer, 2017). His primary research interests include ultra-low power and self-powered systems, near-threshold circuits, widely-energy scalable systems, energy-quality scalable systems, data-driven systems and embedded machine learning, HW security.
He is the Editor in Chief of the IEEE Transactions on VLSI Systems (2019-2020), and the Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2018). He served as Guest Editor of several IEEE journal special issues (TCAS-I, TCAS-II, JETCAS), and as Associate Editor of a number of IEEE and ACM journals. Prof. Alioto is/was Technical Program Chair (ISCAS 2023, SOCC, ICECS, NEWCAS, ICM, PRIME), Track Chair in numerous conferences (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM), and TPC member of others (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.
HD-2c. Body Area Network – Connecting Things Together Around the Human Body
Jerald Yoo (National University of Singapore)
Chronic diseases account for over 1/3 of deaths around the world. To mitigate the impact of such diseases, healthcare paradigm is now shifting from reactive illness management towards proactive and preemptive health management; the goal here is to maintain a healthy life in the first place or to prevent illness from getting any worse by continuously monitoring health during normal daily life. Body Area Network (BAN) is an attractive means for continuous and pervasive health monitoring, yet its unique and harsh environment gives circuit designers many challenges. As human body absorbs the majority of RF energy around GHz band, existing RF radio may not be an ideal for communications between and on-body sensors.
In order solve the issues, this tutorial presents the Body Coupled Communication (BCC)-based BAN. BCC BAN utilizes human body itself as a communication medium, which has orders of magnitude less pathloss when compared to RF based BAN. We will cover three types of BCC-BAN: 1) capacitive coupling, 2) magnetic coupling and 3) galvanic coupling. For each type, we will explorer its channel characteristics, followed by design considerations and transceiver implementation examples. I will then discuss what circuit designers should consider in such non-conventional environments. Low energy circuit techniques to overcome their limitations will also be discussed. We will then will review their various system aspects of the BAN, including powering up the wearables using the wearable BAN.
- Flexible Electrode and Platform: We will first explore flexible platform that enables wearable form factor electrodes and BAN sensor, namely the Planar-Fabric and Polymer Circuit Board.
- BAN-BCC Types: There are largely three types of BCC: 1) capacitive coupling, 2) magnetic coupling, and 3) galvanic coupling. Each type has its own strengths and weaknesses. We will review extensively pros and cons of each approach, with example applications.
- Circuit and Transceiver Design for BCC-BAN: We will study the transceiver implementation with circuit and system aspect design consideration. BCC-specific issues and circuit ideas to overcome such issues will be covered thoroughly. This will be directly related to the each BCC type discussed in Section 2.
- System and Network Formation: Finally, we will cover how to form an energy-efficient BAN with the BCC. Star topology vs. ad-hoc topology will be compared, and the MAC/Network layer design considerations will be covered. After covering the system verification, we will look in to several system examples that use the BCC Network. Finally, the tutorial will conclude with interesting aspects and opportunities that lie ahead.
Jerald Yoo received the B.S., M.S., and Ph.D. degrees in Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively.
From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Since 2017, he has been with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor. He has pioneered research on low-energy body-area-network (BAN) transceivers and wearable body sensor network using planar-fashionable circuit board for continuous health monitoring system. He has authored book chapters in Biomedical CMOS ICs (Springer, 2010) and in Enabling the Internet of Things - From Circuits to Networks (Springer, 2017). His current research interests include low-energy circuit technology for wearable bio signal sensors, flexible circuit board platform, BAN transceivers, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT) and System-on-Chip (SoC) design to system realization for wearable healthcare applications.
Dr. Yoo is an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer. He also served as the IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (2017-2018). He is the recipient or a co-recipient of several awards: the IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015 and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the Vice Chair of IEEE SSCS United Arab Emirates (UAE) Chapter. Currently, he serves as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), ISSCC Student Research Preview (co-chair), IEEE Custom Integrated Circuits Conference (CICC, Emerging Technologies Subcommittee Chair), and IEEE Asian Solid-State Circuits Conference (A-SSCC). He is also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society. He is a senior member of IEEE.