Monday October 12, 18:30-20:00
MT-1. Analog Hardware Approaches for Solving Hard Discrete Optimization Problems - Part I
Room Andalucía 1-2
Yoshihisa Yamamoto (NTT and Stanford), Joachim Wabnig (Bell Labs), Zoltan Toroczkai (University of Notre Dame), Tianshi Wang and Jaijeet Roychowdhury (University of California Berkeley)
Over the last decade, techniques for solving classically difficult (NP-complete and -hard) optimization problems using specialized analog hardware-based approaches have emerged. Such approaches leverage analog dynamics and physics to find good solutions of discrete optimization problems, potentially much faster than classic algorithms. Several of these approaches implement and solve the Ising model, a simple but powerful computational model with origins in the physics of ferromagnetic materials. Many difficult optimization problems can be cast in Ising form; as a result, hardware that solves Ising effectively can be used to solve these problems. This tutorial, by leading researchers in the area, will provide an overview of the field. Approaches to be covered include:
- Quantum Annealing (Wabnig), a technique implemented by D-Wave Systems in 2011 to solve Ising problems in hardware;
- The Coherent Ising Machine (Yamamoto), a machine that uses optical frequency division to encode Ising spins in the phases of light pulses, implementing an Ising machine that also effectively performs quantum annealing;
- Analog SAT Solvers (Toroczkai), which embed the Boolean Satisfiability (SAT) problem in a deterministic, continuous-time analog differential equation setting and rely on analog dynamics to solve them; and
- Oscillator Ising Machines (Wang/Roychowdhury), a classical (non-quantum) technique that implements Ising problems using networks of coupled oscillators and relies on transitioning them between analog and digital modes of operation to find good solutions.
Yoshihisa Yamamoto is Director of NTT Physics & Informatics (PHI) Laboratories, a Senior Vice President of NTT Research, Professor Emeritus at Stanford, and a National Institute of Informatics (NII) R&D Fellow. After his Ph.D (Univ. Tokyo, 1978), he joined NTT Research. He became a Professor of Applied Physics and EE at Stanford in 1992, and a Professor at NII in 2003. Yamamoto’s work led to the Coherent Ising Machine. His distinctions include the Carl Zeiss Research Award, the Nishina Memorial Prize, the IEEE/LEOS Quantum Electronics Award, the Japan Medal with Purple Ribbon, the MIT Haus Lecturer, and the Okawa Prize.
Joachim Wabnig is a Research Scientist in the Maths & Algorithms Group at Nokia Bell Labs (Cambridge, England). Becoming interested in the weird world of quantum mechanics listening to Anton Zeilinger's seminars as an undergraduate in Vienna, he went on to a PhD on the theory of quantum measurement involving nanoelectronic devices (Umeå University, Sweden). After postdoctoral research at the Universities of Oxford and Cambridge, he joined the quantum technologies team at Nokia Research Center, Cambridge, in 2011. He has been working on quantum cryptography, linear optics quantum computing, quantum annealing, binary optimisation and, more recently, on efficient neural networks.
Zoltan Toroczkai is Professor of Physics and CSE at the University of Notre Dame. After his PhD (Virginia Tech, 1997) and postdoctoral work in condensed matter physics (Univ. Maryland), he joined the Los Alamos National Laboratory (LANL) as a Director-Funded Fellow, progressing to regular research staff member and later to Deputy Director of the Center for Nonlinear Studies. In 2006, he joined the Department of Physics at Notre Dame. His research interests include statistical/mathematical physics, nonlinear dynamical systems, complex networks, foundations of computing, and brain neuronal networks. He has 100+ peer-reviewed publications in these areas. He is an APS Fellow.
Tianshi Wang (PhD 2020, Berkeley) is with Google, Inc.. In his doctoral work, he showed that nonlinear oscillators can perform both general-purpose Boolean computation and Ising-model-inspired combinatorial optimization. His interests also include the theory, characterization and compact modelling of novel electronic and multi-domain devices, and their applications in novel computational architectures and paradigms. In 2019, Tianshi received the Bell Labs Prize and the Best Paper Award at UCNC for his work on oscillator Ising machines. He also received Berkeley’s Chua Award in Nonlinear Science in 2017, and its David J. Sakrison Award for "truly outstanding research" in 2019.
Jaijeet Roychowdhury (PhD 1993, Berkeley) is Professor of EECS at Berkeley. His research group's contributions include Ising-based and von Neumann computation using oscillators, novel machine-learning techniques for dynamical systems, theory and techniques for oscillator phase macromodels, injection locking and phase noise, multi-time partial differential equations and techniques for model reduction of time-varying and nonlinear systems. Roychowdhury was cited for "Extraordinary Achievement" by Bell Laboratories in 1996 (for work on MOS homotopies), shared the Bell Labs Prize with Tianshi Wang in 2019, and has (co-)authored eight best/distinguished papers. Roychowdhury co-founded Berkeley Design Automation in 2002. He is an IEEE Fellow.
MT-2. Analog processing by digital gates: fully synthesizable IC design for IoT interfaces
Room España 5
Paolo S. Crovetti, Politecnico di Torino, Orazio Aiello, National University of Singapore
Analog integrated circuits do not take advantage of scaling and are easily the bottleneck in terms of cost and performance in Internet of Things (IoT) sensor nodes integrated in nanoscale technologies. While this challenge is most commonly addressed by devising more “digital friendly” analog cells based on traditional design concepts, the possibility to translate analog functions into digital, so that to implement them by true digital gates, is now emerging as a promising alternative. This last approach, which challenges the idea that “analog circuits will be always needed”, is presented in this tutorial starting from the theoretical background to its application in digital-based operational amplifiers, voltage references, oscillators and data converters integrated on silicon which have proposed in recent literature.
The applicability of the concepts to the design of ICs which are natively portable across technology nodes and highly reconfigurable, thus enabling dynamic energy-quality scaling, as well as a low design effort and a fast time-to-market will be described.
Paolo Crovetti (S’00, M’04) is an Associate Professor with the Department of Electronics and Telecommunications (DET), Politecnico di Torino, Turin, Italy. His research interests are in the fields of analog, mixed-signal and power integrated circuits and electromagnetic compatibility. His recent research activities are focused on non-conventional information processing techniques allowing the fully digital implementations of analog functions and on ultra-low-power IC design for Internet of Things (IoT) applications. Prof. Crovetti is an Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS and a Subject Editor of IET Electronics Letters in the area of Circuits and Systems.
Orazio Aiello (S'06, M'15, SM'19) received the B.Sc. and M.Sc. degrees (cum laude) from the University of Catania, Italy, in 2005 and 2008, respectively and the Ph.D. degree from the Politecnico di Torino, Italy, in 2013. In 2014, he joined NXP Semiconductors, The Netherlands. From 2015 to 2016, he was a Visiting Fellow with The University of Sydney and the University of New South Wales, Australia. In 2015 he got the Marie Sklodowska-Curie Individual and Global Fellowship. Since 2015 he works with the National University of Singapore. His main research interests focus on energy-efficient circuit design, and mostly digital sensor interfaces.
MT-3. Hardware Security in Three-Dimensional Integrated Circuits and Systems
Room España 4
Qiaoyan Yu (Univ. of New Hampshire, USA), Emre Salman (Stony Brook Univ., USA)
Three-dimensional (3D) integration is an emerging technology to ensure the growth in transistor density and performance that is expected from future integrated circuits (ICs). It has been demonstrated that 3D techniques can be leveraged to reduce package size and power consumption while significantly improving communication bandwidth. However, 3D integration technology is a double-edged sword, as it introduces unique and unexplored challenges on managing related hardware security issues. In this tutorial, we will first provide a brief and broad overview of different types of 3D integration technologies. Next, we will summarize the novel opportunities offered by 3D integration for security mechanism. Then, we will highlight potential security vulnerabilities in 3D ICs. To analyze these security challenges, we will formulate new attack models for hardware Trojan insertion and power-based side-channel attacks. Next, we will present the start-of-the-art countermeasures against attacks in 3D ICs and systems. The ultimate goal of this tutorial is to rally the circuits and systems community around the challenge of security threats in 3D chip designs and deployment to highlight recent results and to explain open research problems.
Qiaoyan Yu (S’03-M’11-SM’17) received the Ph.D. degree in Electrical Engineering from the University of Rochester in 2011. Currently, she is Associate Professor in the Department of Electrical and Computer Engineering at the University of New Hampshire. Her research expertise are hardware Trojan detection and mitigation, side-channel attacks and countermeasures, three-dimensional integrated circuits (3D ICs) security, embedded system security, cybersecurity, error control for networks-on-chip, and fault tolerance. Dr. Yu received the National Science Foundation CAREER Award and the Air Force Research Lab Faculty Fellowship in 2017.
Emre Salman (S’03-M’10-SM’17) received the Ph.D. degree in electrical engineering from the University of Rochester, NY, USA in 2009. He is currently an associate professor at the Department of Electrical and Computer Engineering at the State University of New York at Stony Brook. His broad research interests include energy-efficient and secure integrated circuits for a variety of applications ranging from microwatt energy harvesting devices to larger-scale computing systems and emerging integrated circuit technologies. Emre received NSF CAREER Award in 2013, Outstanding Young Engineer Award from IEEE Long Island in 2014, and Technological Innovation Award from IEEE Region 1 in 2018.
MT-4. Flexible and Printed IoT Sensors: Materials, Technology and Selected Applications
Room España 3
Sharmistha Bhadra (McGill University, Canada)
In recent years printed and flexible electronics technology have attracted a significant level of interest in the sensor area due to simplified processing steps, reduced material wastage, low fabrication cost, simple patterning techniques, and realization of electronics on flexible and low-cost substrates. Due to the advantages of printed and flexible sensors, many researchers are considering fabricating the IoT sensors with printed and flexible electronics technology. Although printed and flexible sensors are economically attractive, their operational performance is generally poor. This is significant enough to limit the number of commercially available printed sensors today. Most of the commercially available printed and flexible sensors are NFC tags, glucose and force sensors. From this tutorial, the attendees will understand the concept of printed and flexible sensors and will be able to identify the basic limitations of printed and flexible electronics technology to develop high-performance sensors. They will learn how emerging technologies, new materials and novel circuit topologies can push the limitations of current printed and flexible sensors. Overall, they will acquire the knowledge necessary for the design and development of high-performance low cost printed and flexible sensors. As printed and flexible sensors can play an important role in the growth of IoT, this is high time to arrange this tutorial.
Sharmistha Bhadra joined McGill University in 2016 and is currently an assistant professor. She has published 40 papers and holds 2 patents in the sensor area. Her current research interests are in the area of printed and flexible hybrid electronics, microelectronics, microelectromechanical systems, and sensors and actuators. Her research program at McGill University leverages conventional design and development tools as well as printed electronics technology to find cost-effective and high performance innovative electronic technology. One of her concrete research goals is to use of printed and flexible hybrid electronics technology to develop high-performance sensors and other basic electronic components.
MT-5. Get Rid of RF Isolators! Advanced Reflectionless High-Frequency Passive Components for Emerging Compact/Energy-Efficient RF Front-Ends
Room España 2
Roberto Gómez-García (University of Alcalá, Spain)
RF isolators are usually employed in RF front-ends chains to prevent active stages to be damaged by the presence of RF signal-power reflections created by the passive stages (e.g., pre-select RF bandpass filters) in their out-of-band regions. Indeed, such RF signal-power reflections may induce RF amplifiers to operate in the non-linear regime or to create additional undesired mixing products in frequency-conversion stages, which may result in the malfunctioning of the entire RF transceiver. Whereas passive and active RF isolators avoid this problem, this is done at the expense of higher size/volume and increased DC power consumption, respectively, as well as higher cost. A more-efficient solution that is recently gaining considerable research attention may be the exploitation of “reflectionless” RF passive devices, where the out-of-band signal energy is dissipated inside the circuit instead of being reflected back to the source so that RF isolators are no longer needed. The purpose of this Mini-Tutorial is to familiarize the audience with the emerging topic of reflectionless/absorptive RF passive components, which may result in considerable benefits for emerging RF front-end chains of new wireless systems (e.g., 5G and beyond) in terms of energy-efficiency/DC-power-saving, overall size/volume, and cost. After introducing the problem of RF power reflections in RF front-end chains and classic solutions to circumvent them with their limitations, the main strategies for the design of reflectionless RF passive components as new paradigms are described. This includes both mono-functional RF components (e.g., bandpass filters with static and frequency-adaptive behavior) as well as multi-functional RF devices in which several RF-analog-signal-processing actions are co-integrated together (e.g., filtering and power division or impedance transformation). Experimental results of several proof-of-concept demonstrators in a variety of RF technologies (e.g., planar, acoustic-wave-based, and 3-D ones) will be also presented.
Roberto Gómez-García is an Associate Professor at the University of Alcalá, Spain, and his research interests are in the areaS of RF/microwave multi-functional and reconfigurable passive components, as well as RF sensors and SDR systems. He is currently an “IEEE Circuits and Systems Society (CAS-S) Distinguished Lecture” for the term 2020-2021 and was the recipient of the “2016 IEEE Microwave Theory and Techniques Society (MTT-S) Outstanding Young Engineer Award”. He serves and has served as Associate and Guest Editor for several IEEE journals of MTT-S and CAS-S, and as a member of the Technical Program Review Committee of various IEEE conferences.
Tuesday October 13, 18:30-20:00
MT-6. Analog Hardware Approaches for Solving Hard Discrete Optimization Problems - Part II
Room Andalucía 1-2
Yoshihisa Yamamoto (NTT and Stanford), Joachim Wabnig (Bell Labs), Zoltan Toroczkai (University of Notre Dame), Tianshi Wang and Jaijeet Roychowdhury (University of California Berkeley)
See details in MT-1.
MT-7. Design Techniques for Reliable High Voltage Gate Drivers for Automotive Applications
Room España 5
Sri Navaneeth Easwaran (Texas Instruments Inc, Dallas, Texas USA), Samir Camdzic (Texas Instruments), Robert Weigel (Univ. of Erlangen-Nuremberg, Germany)
Gate drivers are commonly used in several electronic applications to drive power transistors that deliver high current outputs. For medium-range currents ~ 1A to 5A, the State of the Art is to integrate these power MOSFETs along with their gate drivers (including charge pumps or boost converters that supply the gate drivers ) whose operating voltage ranges from 5V to 60V. Reliability of these integrated gate drivers and power transistors is a key factor to meet the high-quality demands of the Automotive and Industrial applications. In this tutorial, challenges related to the design and reliability of the High Side (HS) drivers, configurable HS and Low Side (LS) drivers are discussed. Reliability is ensured by exposing the gate drivers and powerFETs to several short to ground and battery cycles. A new Design FMEA (Failure Mode Effect Analysis) flow for designing these drivers for fault tolerance is presented. These drivers, powerFETs are tested with similar conditions for several million pulses for robustness. This type of testing methodology has an additional impact to design and test for System On Chips (SOCs) where multiple drivers are integrated on a single substrate.
In addition, these gate drivers need to drive wide range of inductive loads from 1μH to 100μH and in some scenarios need to handle up to 3mH inductances. These gate drivers have to be thoroughly designed for robustness w.r.to. Electrical and Thermal Safe Operating Area (SOA) and should never be switched ON or OFF too fast. This has an impact on EMI (Electro Magnetic Performance). This tutorial discusses the disadvantages of fast switching as several quiet circuits become victims due to EMI, package inductances and addresses the different solutions including spread spectrum techniques and digitally assisted design methodology for reducing EMI. Structures for the proof of concept are simulated and measured. This tutorial will be valuable for the design community to carefully design several low noise safety-critical circuits for automotive and industrial applications.
Samir Camdzic (PhD) joined Texas Instruments (TI) in 1996 as a design engineer. He has worked on squib drivers, electrical power steering, tire pressure sensor ICs for automotive applications. He has worked on consumer ICs for streaming audio applications, USB / IEEE1394 / short distance wireless peripheral interfaces with embedded controllers and currently working as a systems lead responsible for definition of integrated safety power ICs for Radar and automotive safety applications. Before joining TI he was with IBM as a design team member of Advanced Space Application group. He is a TI Member Group of Technical Staff.
Sri Navaneeth Easwaran, Senior Member IEEE, received his Bachelor’s (1998, Bharathidasan University), Master’s (2006, University Twente) degrees in Electrical Engineering and Dr. –Ing. degree from University of Erlangen-Nuremberg in 2017. He worked at SPIC Electronics, STMicroelectronics, Philips Semiconductors between 1998 and 2006. From 2006 he is with Texas Instruments (TI) where he was the design lead for airbag squib driver ICs. He has also designed high voltage tolerant circuits for automotive ICs. He is a TI Senior Member Technical Staff, has 20+ granted patents and 14 publications. He has offered tutorials on Automotive design at IEEE Conferences.
Robert Weigel, Fellow IEEE and Fellow ITG, is Full Professor at the University of Erlangen-Nuremberg, Germany. He co-founded several companies some of which were later overtaken by Infineon, Intel and Apple, respectively. He has been engaged in microwave electronic circuits and systems and has published more than 1200 papers. He received the 2002 VDE ITG-Award, the 2007 IEEE Microwave Applications Award, the 2016 IEEE MTT-S Distinguished Educator Award, the 2018 Distinguished Service Award of the EuMA and the 2018 IEEE Rudolf Henning Distinguished Mentoring Award. He has been Distinguished Microwave Lecturer, MTT-S AdCom Member, and the 2014 MTT-S President.
MT-8. Offset Mitigation in Low-Voltage Sense Amplifiers and its Implication on SRAM Design and Test
Room España 4
Manoj Sachdev (University of Waterloo, Canada)
Static Random Access Memories (SRAMs) often occupy a significant area of contemporary Systems on Chip (SoC) integrated circuits (ICs) and therefore determine their energy consumption, yield, and reliability. The sense amplifier (SA) is a critical SRAM circuit that requires careful design. The offset in the SA does not scale well with technology scaling and has become an impediment to realizing energy efficient SRAMs. Additionally, the offset in SAs can also give rise to intermittent failures in SRAMs that are difficult to detect through traditional march test algorithms.
This tutorial is divided into two parts. The first part focuses on SA design and contrasts techniques for mitigating SA offset voltage. The second part addresses SRAM design and test considerations for the SA offset voltage. Traditional approaches of SRAM testing are inadequate to cover SA offset related failures, and we highlight Design for Testability (DfT) techniques for detecting such failures. The tutorial draws data from several different publications, and from several test chips designed by the presenter and his graduate students.
Manoj Sachdev is a professor in the ECE department, at the University of Waterloo, Canada. He has contributed to 5 books, more than 30 patents, and over 225 journal and conference publications. He, his students, and his colleagues have received several international research awards. He received the best paper award at 1997 IEEE DATE conference. In 1998, he received the honorable mentioned award in the IEEE International Test Conference. In 2011, he was a recipient of the best paper award in IEEE ISQED, and in 2015, he was a recipient of the best poster award in IEEE CICC. Professor Sachdev is an IEEE Fellow, Fellow of Canadian Academy of Engineering.
MT-9. Energy-efficient bio-inspired devices and architectures accelerate route to brain-like computing
Room España 3
Siegfried Karg (IBM Research, Zurich), Aida Todri-Sanial (LIRMM-CNRS, France), Bernabé Linares Barranco (IMSE-CNM, Sevilla, Spain), M.J. Avedillo (IMSE-CNM, Sevilla, Spain), T. Serrano-Gotarredona (IMSE-CNM, Sevilla, Spain)
Neuro-inspired computing employs technologies that enable brain-inspired computing hardware for more efficient and adaptive intelligent systems. By mimicking the human brain and nervous system, these computing architectures are excellent candidates for solving complex and large-scale associative learning problems. The mini-tutorial is based on the recently EU-funded NeurONN project. In NeurONN, we are developing an alternative neuromorphic computing paradigm based on energy-efficient devices where the information is encoded in the phase of coupled oscillating neurons or an oscillatory neural network (ONN). In this mini-tutorial, we aim to cover various aspects from devises, architecture design to algorithms to implement ONNs.
Siegfried Karg is Research Staff Member at IBM Research Zurich. He holds a Ph. D. degree in physics from Univ. Bayreuth (Germany). His current research fields are on 1D electronic properties of nanostructures and brain-inspired computing applications.
Aida Todri-Sanial is a Director of Research at CNRS, France. She holds a Ph. D. degree in Computer Engineering from Univ. of California Santa Barbara. Her current research fields are on 1D/2D nanomaterials for devices and circuits, and design of novel computing paradigms such as neuromorphic and quantum computing. https://www.lirmm.fr/~todri
Bernabe Linares Barranco is a Full Professor at the Institute of Microelectronics of Seville. His research is on circuit design for telecommunication circuits, VLSI emulators of biological neurons, VLSI neural-based pattern recognition systems, hearing aids, precision circuit design for instrumentation equipment, bio-inspired VLSI vision processing systems, VLSI transistor mismatch parameters characterization, and memristors-based learning neuromorphic architectures.
Maria J. Avedillo is a Full Professor in the Department of Electronics and Electromagnetism of the University of Seville (US) and a member of the Instituto de Microelectrónica de Sevilla (IMSE), currently a joint centre of CSIC and US. Her research is focused on the study of VLSI integrated circuit design and test methodologies, the development of logic synthesis algorithms, the study of non-Boolean logic, both as regards the electrical realization of its components, as well as its use as a computational model in digital design and, more recently, in the design of circuits using emerging devices.
MT-10. Design of Ultra-Low-Power Discrete-time receivers for the Internet of Things
Room España 2
Sandro Binsfeld Ferreira (Univ. do Vale dos Sinos, São Leopoldo, Brazil), Robert Bogdan Staszewski (Univ. College Dublin, Ireland)
Internet of things imposes severe ultra-low-power requirements for radio frequency transceivers. Battery life is critical in these applications and can be extended by lowering supply voltage or power consumption of the radio. In the receiver part, the analog section is the most power-hungry subsystem and has received a lot of attention lately, mainly in an analog continuous-time point of view. This traditional approach, however, is not always friendly to voltage supply reduction and usually suffers from technology scaling. Another important aspect of this required low power solution is a complete integration of the RF building blocks in order to reduce system costs.
Recent advances in discrete-time receiver design offer a new alternative, with simpler and scalable analog circuits, easy calibration of intermediate frequency and band-pass selection based on capacitor ratios, which are less affected by process variations. New discrete-time receivers are based on passive charge- domain switched-capacitor topologies and the accurate control of sampling rates, both of which benefit from technology scaling and enable easier-to-design low- power solutions. Novel switched-capacitor architectures present highly selective band-pass filters and enable saw-less solutions for either low-power or high-performance applications. Additionally, with the on-chip integration of these high- quality-factor switched-capacitor filters, the super-heterodyne receiver can be easily adopted with fewer issues regarding flicker noise, second-order linearity, and time-varying DC offsets. This tutorial presents the advances in discrete-time receivers as well as the changes in the design approach which are illustrated with an ultra-low-power state-of-the-art discrete-time architecture, discussed in detail.
Robert Bogdan Staszewski received his PhD from University of Texas at Dallas in 2002. In 1995, he joined Texas Instruments (TI) in Dallas. From 1995 to 1999, he was involved in advanced CMOS read channel development. In 1999, he co-started the Digital RF Processor (DRP) Group in TI with a mission to invent new digitally intensive approaches to traditional RF functions for integrated radios in deeply scaled CMOS technology. In 2009, he joined Delft University of Technology, Netherlands, and appointed to Full Professor in 2013. Since 2014, he has been a Full Professor with University College Dublin (UCD), Ireland.
Sandro Binsfeld Ferreira received his PhD degree in Microelectronics from the Federal University of Rio Grande do Sul, Brazil, in 2016. From 2009 to 2014, he was an RF IC Design Instructor with the IC Brazil Program. In 2014, he was a Visiting Researcher with the Delft University of Technology, The Netherlands. From 2014 to 2016, he was consulting for the RF Group of TSMC, Taiwan, involved in the design of discrete-time receivers for BLE. From 2017 to 2018, he was consulting for Orca Systems, San Diego, US. Since 2011, he is a Professor of Electrical Engineering at Unisinos University, Brazil.